The present invention relates to an active matrix liquid crystal display, and more particularly to a driving circuit of the point at a time type active matrix liquid crystal display in which charge time of all pixels connected to the end of the gate bus lines is the same so that the quality of a picture is improved.
There, in general, are two driving method of the active matrix LCD(AMLCD) arrangements for driving the LCDs, the line at a time type and the point at a time type. In the line at a time type, a signal voltage is simultaneously applied to pixels connected to one scan bus line and then stored to each pixel while the signal voltage is being applied to one scan bus line. To drive the LCD, therefore, sample and hold circuits which charge the signal voltage corresponding to one scan bus line and then apply to the pixels are needed. In addition, since the distortion of the charged signal voltage must be eliminated, the drive circuit becomes complex. Accordingly, the line at a time type drive circuit is used for an amorphous silicon thin film transistor(a-Si TFT) LCD in which driving integrated circuits(ICs) are attached around the periphery of a liquid crystal panel.
In the point at a time type, the signal voltage is orderly applied to the scan bus lines according to the order of the signal. This type, thus, is employed to poly silicon(p-Si) TFT LCD in which the driving circuit is manufactured on the liquid crystal panel.
FIG. 1 is a view showing the conventional circuit of the point at a time type AMLCD. In this figure, reference numbers 10 and 20 indicate a data driving circuit and a gate driving circuit, respectively.
The data driving circuit 10 comprises a shift register 11 having n output lines, a buffer 12, for outputting the signal input from the shift register 11, having n output and input lines, and pass gate transistors SW1, . . . , SWn to be driven by the signal inputted from the buffer 12. The gates of the pass gate transistors SW1, . . . , SWn are connected to the output lines of the buffer 12, the sources are connected to a visual signal input line 13, and the drains are connected to data bus lines Y1, . . . , Yn of a data output representing unit 30.
The gate driving circuit 20 comprises a shift register 21 having m output lines and a buffer 22, for outputting the signal input from the shift register 21, having m output and input lines. The output lines of the buffer 22 are connected to scan bus lines X1, . . . , Xm of the data output representing unit 30.
The data output representing unit 30 includes an orthogonal array of m horizontal(or, vertical) scan bus lines X1, . . . , Xm and n vertical(or, horizontal) data bus lines Y1, . . . , Yn with a pixel formed at each intersection, where m and n are related to vertical and horizontal resolution of the LCD, respectively.
At the intersection of the scan bus lines X1, . . . , Xm and the data bus lines Y1, . . . , Yn, in the pixels, the TFTs 31 of which the sources are connected to the data bus lines Y1, . . . , Yn. The drains of the TFTs 31 are connected to one electrode of storage capacitors 32, that is, a pixel electrode, and one electrode of an auxiliary storage capacitor 33 in parallel.
The storage capacitor 32 consists of common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate, TFT array substrate, which are facing with liquid crystal. Further, the auxiliary storage capacitor 33 is connected to the storage capacitors 32 in parallel to store charge, so that the flicker caused by the leakage of the TFT is decreased and the variation of the pixel voltage caused by the interference of the signal of the scan bus lines is also decreased.
Since the TFT 31, the storage capacitor 32, and the auxiliary storage capacitor 33 are formed in each pixel, the total number of these is horizontal resolution(m).times. vertical resolution(n), respectively.
Accompanying FIG.1 and 2, the operation of driving circuit in the conventional AMLCD is described in detail as follows. In this case, only the pixel connected to the ith scan bus line is described for convenience.
When the horizontal synchronous signal is applied to the gate driving circuit 20, not shown in figures, the gate driving signal Vgi which is applied to the ith scan bus line from the shift register 21 and the buffer 22 of the gate driving circuit 20 is activated. The gate driving signal Vgi is activated for the period that the visual signal Vs is being applied to all pixels Pi1, . . . , Pin formed at the intersection of the ith scan bus line Xi and the data bus lines Y1, . . . , Yn. Thus, the TFTs of pixels Pi1, . . . , Pin connected to the ith scan bus line Xi is turned on for this period.
Subsequently, the visual signal Vs is inputted to the data bus lines Y1, . . . , Yn through the visual signal input line 13, and at the same time the data driving signal Vd1 that is activated through the shift register 11 and the buffer 12 of the data driving circuit 10 for a short period is inputted to the first pass gate transistor SW1, so that the first pass gate transistor SW1 is turned on. For the period that the first pass gate transistor SW1 is turned on, the visual signal Vs is inputted to the storage capacitor 32 and the auxiliary storage capacitor 33 through the first data bus line Y1 and the TFT 31.
When the data driving signal Vd1 applied to the first pass gate transistor SW1 is not activated, the first data bus line Y1 maintains a uniform voltage V11. The first data bus line Y1 maintains this uniform signal, in other words, until the new activated data driving signal Vd1 is applied to the first data bus line Y1 again. Further, the pixel voltage Vp1 of a uniform level, applied from the first data bus line Y1, is kept in the storage capacitor 32 until the next signal has been applied to the pixel.
By de-activating of the first data driving signal Vd1 and activating of the second data driving signal Vd2, the same operation that is carried out in the first data bus line Y1 and the pixel Pi1 is repeated in the second data bus line Y2 and the pixel Pi2.
Repeating this behavior n times, when the gate driving voltage Vgi applied to the ith scan bus line Y1 is not activated and then the next horizontal synchronous signal is applied to the (i+1)th scan bus line X(i+1), the gate driving voltage Vg(i+1) applied to the scan bus line is activated, so that the above behavior is repeated.
While the data driving signal Vdn for driving the pass gate transistor SWn connected to the nth data bus line Yn is activated in the activated state of the gate driving signal Vgi applied to the ith scan bus line Xi, in the aforementioned drive circuit, the visual signal Vs is sufficiently applied to the nth data bus line Yn as the waveform shown in FIG.2. However, because the pixel TFT 31 is smaller than the pass gate transistor, the current driving capacity of the pixel TFT 31 is smaller than that of the pass gate transistor. To store a sufficient signal Vs to the storage capacitor 32, therefore, the signal Vs is continuously stored for a time. In this case, however, the gate of the pixel TFT 31 is turned off before the sufficient signal Vs is not applied to the pixel, so that the signal Vs is partially stored to the storage capacitor 32 and then the signal Vs is distorted.
When the 60 signals is applied to each pixel per 1 second, the activation time of the gate driving signal Vgi is 1/60.times.1/m(sec) and the activation time of the data driving signal Vdj, where j=1,2, . . . , n, is 1/60.times.1/m.times.1/n(sec).
The pass gate transistor SWj is turned on by the data driving signal Vdj to apply the visual signal Vs to the data bus line Yj, and at the same time the visual Vs is delivered to the pixel Pij through the pixel TFT 31. However, because the visual signal Vs of desired magnitude cannot be applied to the pass gate transistor SWj and pixel TFT 31 by the small current delivering capacity of the pass gate transistor SWj and the pixel TFT 31, the data bus line Yj and the pixel Pij require the same charge time for perfect charge. Since the charge time of the pixel, into which the signal is applied through the pixel TFT 31, is longer than that of the data bus line Yj, in addition, the visual signal Vs is continuously charged into the pixel after the disable of the data driving signal Vdj.
The gate driving signal Vgi, for turning on the pixel TFT 31, is kept in an activated state until the last data driving signal Vdn has been de-activated. Accordingly, the visual signal Vs is delivered to each pixel from the data bus line for 1/60.times.1/m-1/60.times.1/m.times.1/n(sec) after non-activation of the data driving signal Vdj applied to the jth data bus line Yj.
In the first pixels connected to each scan bus line, for example, after the data driving signal Vdj is applied to the data bus line Yj and then disabled, there is a remaining time, 1/60.times.1/m-1/60.times.1/m.times.1/n(sec), that the visual signal Vs is delivered to the pixels. In the last pixels Pin, however, the visual signal Vs is applied to the pixels for applying time of the data driving signal Vdj to the data bus line. Therefore, there is a problem that the sufficient signal cannot be applied to the pixels, in which the visual signal is sampled late, and then the quality of a picture is deteriorated.